The present invention relates to phase-locked loops (PLLs) generally and, more particularly, to a charge pump that may be used in a PLL.
Phase-locked loop (PLL) based clock recovery systems often employ charge pumps as internal circuitry. A low static phase offset in the PLL leads to longer possible transmission lengths due to the more ideal sampling point of the incoming data.
Referring to FIG. 1, a circuit 10 illustrating a typical charge pump is shown. The circuit 10 receives a signal PUMPUP and PUMPDN, which can be divided into pairs of signals PUMPUPP and PUMPUPN, and PUMPDND and PUMPDNN, respectively. The non-filter drain of the current steering differential pairs is tied to a fixed voltage (i.e., VMID) which is most likely different from the other drain of the differential pair (i.e., FILTU and FILTD). When the signal PUMPUP and the signal PUMPDN transition, the sources of the differential pairs (i.e., NSRC_P_U, NSRC_N_U, NSRC_P_D, and NSRC_N_D) move from one voltage to another, based upon the difference between the signals FILTU and FILTD and the signal VMID. The greater the difference between the signals FILTU/FILTD and the signal VMID, the more the source nodes move. The net result is a mismatch between the signal FILTU_PUMP and the signal FILTD_PUMP. The common mode correction circuit (i.e., the transistors connected to the signals CM_PBIAS and CM_BIAS) may cancel some not all the mismatch. The rest of the mismatch results in static phase offset.
Another disadvantage with the circuit 10 is the lack of cascoded current sources. Due to the low output impedance of a single device, noticeable current variations can occur with changes in the signals FILTU and FILTD. This can also result in static phase offset. The use of the signal VMID on the gate of one side of the differential pair reduces the operating frequency of the pump, which becomes significant at lower voltages. Using differential switching increases the operating frequency of the device, or allows the same operating frequency at lower operating voltages. In addition, two common mode signals are needed (i.e., CM13 PBIAS and CM_NBIAS). This increases the complexity of the common mode control circuit.
Referring to FIG. 2, a circuit 50 is shown illustrating another conventional buffering method. The circuit 50 comprises a voltage source 52, a voltage source 54, a switch S1, a switch S2, a switch S3, a switch S4 and a comparator 56. The circuit 50 is a single-ended system, which is more sensitive to voltage supply noise and has a smaller dynamic range of operation when compared with the circuit of FIG. 1. The smaller dynamic range of operation requires a voltage controlled oscillator (VCO) to have a higher gain, which in turn increases the noise sensitivity.
The present invention concerns a circuit and method comprising a charge pump having a first and a second differential element. The charge pump may be configured to generate a first and a second output signal in response to the first and second differential elements. The first differential element may comprise (i) a first unity gain buffer and (ii) a first and a second transistor pair configured to receive a first and second control signal. The second differential element may comprise (i) a second unity gain buffer and (ii) a third and a fourth transistor pair configured to receive the first and second control signals. The first and second unity gain buffers may stabilize the source nodes of each of the transistors pairs.
The objects, features and advantages of the present invention include a charge pump that may be used in a phase-locked loop that may provide (i) reduced static phase offset,(ii) fewer noise sources, (iii) an increased operating frequency that may compensate for lower supply voltages, (iv) lower voltage operation, and (v) may be implemented using a smaller die area.